1. Field of the Invention
The present invention relates to a display apparatus, which includes a voltage control circuit to transfer the coarse and fine signals from a microcomputer to a PLL (phase-locked loop) circuit to adjust the pixel clock signal for a display apparatus.
2. Description of the Related Art
A display apparatus with multiple display modes includes a microcomputer to select a display mode based on the horizontal and vertical synchronizing signals and the analog video signal received from a host. The PLL circuit includes a phase detector, low pass filter, charge pump circuit, voltage-controlled oscillator and frequency divider, to generate the pixel clock signal under the control of the microcomputer. The microcomputer controls the pixel clock signal to adjust the phase and frequency of the clock signal supplied from the PLL circuit to the analog to digital (A/D) converter according to the selected display mode. The A/D converter samples the analog clock signal corresponding to the display mode in response to the pixel clock signal of the PLL circuit.
A display apparatus exemplary of the related art includes a microcomputer, a PLL circuit and a voltage control circuit connected therebetween to select a display mode according to the horizontal and vertical synchronizing signals and the video signal received from the host. The microcomputer generates the control signals Coarse and Fine to control the pixel clock signal D.sub.-- clk of the PLL circuit according to the display mode. Namely, the microcomputer generates the coarse control signal Coarse to adjust the phase of the sampling clock signal of the A/D converter and the fine control signal Fine to delay the phase of the sampling clock signal according to the display mode.
However, when the coarse control signal Coarse is generated with the source voltage of the fine control signal being applied to the PLL circuit, the charge pump circuit of the PLL is stimulated so as to alter the dividing number of the frequency divider of the PLL circuit over the locking range to stop the loop feedback, since the voltage of the fine control signal Fine is greater than that of the coarse control signal Coarse. This can result in destruction of the integrated circuit (IC) of the PLL circuit or malfunction of the display apparatus.
U.S. Pat. No. 4,988,955 entitled Phase-locked Loop Apparatus, to Horie discloses a clock signal having a predetermined frequency output from a clock generator and a signal output from a voltage controlled oscillator (VCO) and supplied through a frequency divider which are supplied to a phase detector. An output from the phase detector is supplied to a loop filter. The loop filter supplies a voltage in accordance with an output from the phase detector to a first control voltage terminal of the VCO and to a phase lock-in circuit. The phase lock-in circuit supplies a voltage in accordance with an output voltage from a loop filter to a second control voltage terminal of the VCO. In the VCO, the sensitivity of the first control voltage terminal is lower than that of the second control voltage terminal, i.e., a rate of change in output frequency with respect to a change in second control voltage is higher than that of the first control voltage. A phase lock detector for detecting whether or not the PLL apparatus is set in a phase-locked state is also connected to the phase lock-in circuit. When the phase lock detector detects a phase-locked state, a trigger signal is supplied to a power turn off circuit that turns off a power source Vi. The power source Vi is connected to the clock generator, the phase detector, a part of the phase lock-in circuit, the phase lock detector, and the frequency divider. Also, power is always supplied from a power source Vc to the remaining circuit of the phase lock-in circuit.
U.S. Pat. No. 5,151,665 entitled Phase-Lock-Loop System with Variable Bandwidth and Charge Pump Parameters, to Wentzler discloses a phase lock loop frequency synthesizer capable of handling both analog and digital transmission. The synthesizer includes a reference signal source, a phase detector coupled to the reference signal source, a phase lock loop filter coupled to the phase detector, and a voltage controlled oscillator coupled to the phase lock loop filter for providing an output and a feedback signal to the phase detector. The phase lock loop filter includes a charge pump coupled to the phase detector for providing a phase lock signal to a charge pump output node, the phase lock signal being variable in response to a bandwidth control signal, and a filter coupled to the charge pump for filtering the phase lock signal at a given bandwidth, the bandwidth being variable in response to the bandwidth control signal.
U.S. Pat. No. 5,459,755 entitled PLL Circuit, to Iga et al. discloses a PLL circuit wherein a delay circuit of a phase comparator receives a supply current from a first variable current source and changes a delay time in negative correlation with the amount of the supply current, and the first variable current source changes the amount of the supply current to the delay circuit in accordance with the indication of a control signal serving as a supply current control signal for a second variable current source and a third variable current source of a charge pump circuit. Changes in the delay time of the delay device of the phase comparing device are adapted such that the delay time changes as the amount of current of the phase comparison voltage signal of the charge pump circuit changes, permitting reduction in lock-up time.
U.S. Pat. No. 5,534,821 entitled Charge Pump Circuits for PLL Frequency Synthesizer, to Akiyama et al. discloses a PLL frequency synthesizer, which includes a voltage controlled oscillator, and a comparison frequency divider for dividing a frequency of the output signal from the voltage controlled oscillator to output a comparison signal. A phase comparator in the synthesizer compares a phase of a reference signal to be fed thereto with a phase of the comparison signal, and generates first and second phase difference signals, based on the compared result. The synthesizer further includes a charge-pump circuit that is operated based on the first and second phase difference signals, and has an output terminal connected to the voltage controlled oscillator. The charge-pump circuit includes a first bipolar transistor connected between a high-potential power supply and the output terminal, and a second bipolar transistor connected between a low-potential power supply and the output terminal. The first and second bipolar transistors are controlled based on the first and second phase difference signals, respectively. At least one of the first and second bipolar transistors is an emitter-follower type. In another embodiment, a node is provided between two switches formed by CMOS transistors, to serve as an output terminal of the charge-pump circuit. In a further embodiment, two PMOS transistors are provided as switches, and a node is provided therebetween to serve as an output terminal of the charge-pump circuit.